In switch intensive chips such as field programmable gate arrays (FPGAs) chip area requirements dictate the use of N-channel only switches instead of complementary (P-channel and N-Channel) switches. The use of N-channel only switches results in less than rail to rail signal swings since the voltage out of a N-channel switch is (Vgate-Vthreshold).
When an CMOS inverter is driven from this less than full voltage swing signal, the P-channel device in the inverter is never turned completely off. This results in an undesirable DC current from the output of the inverter. One well known way of dealing with this unwanted current is to add a weak feedback inverter to raise the input level to the main inverter to Vdd and thereby allow the P-channel device in the inverter to shut off completely.
FIG. 1 illustrates a prior art multiplexor which uses a feedback inverter to restore the input level to the main inverter. As shown, four N-channel switches 101, 103, 105 and 107 are connected to form a 4 to 1 multiplexor as is known in the art. Input signals IN1-IN4 are the signal inputs to the N-channel switches 101-107 respectively. Select signals S1-S4 control the gates of the N-channel switches 101-107, respectively, and serve to select which, if any, of the N-channel switches are turned to thereby allow the associated input signal to pass through the multiplexor.
The output of the multiplexor, Node A, feeds a main inverter 109. This inverter is designed as a standard CMOS inverter with a P-channel pull up transistor and a N-channel pull down transistor. The output of the main inverter becomes the circuit output 111.
A weak feedback inverter 113 is provided which has an input connected to the output of the main inverter. The output of the weak inverter is connected to the input of the main inverter (Node A). Inside the weak inverter is a two transistor CMOS inverter with the pull up and pull down transistors sized such that the output of the weak inverter can be overpowered by any of the N-channel switches 101-107 so the input to the main inverter can change. The P-channel pull up transistor in the weak inverter serves to pull up Node A to Vdd when a logic "1" is output on Node A by one of the N-channel switches.
While this circuit works generally, the downside of this design is the weak inverter changes the input impedance of the N-channel switches 101-107. While a typical CMOS transistor has an input of approximately 10.sup.14 ohms, since the output of the weak inverter is connected to Node A, the input impedance as seen by a device connected to any of the inputs IN1-IN4 is approximately (30*10.sup.3) ohms. In FPGAs where the fanout may be very large and the series resistance of long interchip interconnect lines may be high, this low input impedance becomes a problem. In particular a transistor driving one of the N-channel switch inputs may not be able to supply the current required to drive the input at high speed, if at all.
Therefore what is needed in the industry is a multiplexor which allows for the use of N-channel switches but retains a high impedance on the inputs to the switches.